[HDLBits] Dff

1. 문제 및 설명

•  하나의 D 플립플롭을 만드시

 

2. 모듈 정의

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );

 

 

 

3. 답

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments
    
    always@(posedge clk)
        begin
            q <= d;
        end

endmodule