[HDLBits] Count clock

1. 문제 및 설명

• AM/PM 표시가 있는 시계를 설계하시오.
  
  • reset: 시계를 12:00 AM으로 초기화
  • pm: AM일 때 0, PM일 때 1
  • hh, mm, ss는 각각 시간, 분, 초를 나타내는 BCD 값이다

 

2. 모듈 정의

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss);

 

 

 

3. 답

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    wire upper_ss, upper_mm, upper_hh;
    wire upper_sm, upper_mh;
    wire reset_time_ss, reset_time_mm, reset_time_hh;
    wire [7:0] wire_hh;

    
    assign upper_ss = (ss[3:0]==4'd9);
    assign upper_mm = upper_ss&(mm[3:0]==4'd9);
    assign upper_hh = upper_ss&upper_mm&(wire_hh[3:0]==4'd9);  
    
    assign reset_time_ss = (reset|upper_sm);
    assign reset_time_mm = (reset|upper_mh);
    assign reset_time_hh = (reset|(wire_hh == 8'h11&upper_mh));
    
    assign upper_sm = (ss == 8'h59);
    assign upper_mh = (mm == 8'h59&upper_mm&upper_sm);
    
    BCD_Counter s0 (clk, reset, ena, ss[3:0]);
    BCD_Counter s1 (clk, reset_time_ss, upper_ss&ena, ss[7:4]);
    BCD_Counter m0 (clk, reset, upper_sm, mm[3:0]);
    BCD_Counter m1 (clk, reset_time_mm, upper_mm&upper_sm, mm[7:4]);
    BCD_Counter h0 (clk, reset_time_hh, upper_mh, wire_hh[3:0]);
    BCD_Counter h1 (clk, reset_time_hh, upper_hh&upper_mh, wire_hh[7:4]);
    
    assign hh = (wire_hh == 8'd0)?8'h12:wire_hh;  
    
    always@(posedge clk)
        begin
            if(reset)
                begin
                    pm <= 1'b0;
                end
            else
                begin
                    pm <= (hh == 8'h11 && mm == 8'h59 && ss == 8'h59)?!pm:pm;
                end
        end

endmodule

module BCD_Counter(
	input clk,
	input reset,
    input ena,
    output reg [3:0] q
	);
	
	always @(posedge clk)
        begin
            if (reset || (q == 9&ena))	// Count to 10 requires rolling over 9->0 instead of the more natural 15->0
                begin
                    q <= 0;
                end
            else if(ena)
                begin
                    q <= q+1'b1;
                end
            else
                q <= q;
        end
        
	
endmodule